TILERA's TILE64 multicore processor

TILE64 multicore processor is announced by TILERA. Compare to Intel's Terascale research prototype, TILE64 not only contains similar number of cores but also has a lot of features.

Amazingly similar, TILE64's interconnect is mesh network which has better scalability than crossbar and better performance than ring. TILE64 features 5 meshes: 2 dedicated for data transfer between tiles and memory (I guess cache-to-cache transfer too.) and other 3 for application use.

The core of each tile is a full featured general-purpose processor compared to other startups' annouced primitive cores. It has not only cache hierarchy but also virtual memory support (MMU and TLB.) The core itself is a 3-way VLIW pipeline. But, most likely, the core should have no FP support considering its current process and targeted applications. The spec says it has totally 5MB cache, each tile likely has 8KB I-cache and 8KB D-cache and 64KB L2 cache (or cache tile.)

Interestingly, TILE64 provide cache coherence and shared L2 cache. It is still unclear how the cache is maintained coherent. But to delivery performance of TILE64, cache hieararchy won't be used for the main data flow due its high latency possibly. Dedicated mesh networks among tiles should be used instead to minimize the cache coherence overhead.

TILE64 provides also friendly developing environment. Linux is ready to run on TILE64.

Till now, only Sun's Niagara2 has comparable features to TILE64 but with a flat memory hierarchy. It is interesting which one is better suited for network processing.